Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization

Su, YC; Huang, SY

Huang, SY (通讯作者),Natl Tsing Hua Univ, Elect Engn Dept, Hsinchu 30013, Taiwan.

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023; 42 (8): 2761

Abstract

A delay-locked loop (DLL) circuit is indispensable for clock synchronization in a chip incorporating several heterogeneous dice. It has been shown pre......

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