A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line

Park, H; Sim, J; Choi, Y; Choi, J; Kwon, Y; Park, S; Park, G; Chung, J; Kim, KM; Jung, HK; Kim, H; Chun, J; Kim, C

Kim, C (corresponding author), Korea Univ, Dept Elect Engn, Seoul 02841, South Korea.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (6): 1886

Abstract

A 1.3-4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable delay line is designed using a 28 nm ......

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