A Clock Interpolation Structure Using DLL for Clock Distribution in ADC

Zhu, SJ; Wang, Y; Ye, F; Xu, J

Xu, J (reprint author), Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China.

2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2017; ( ): 769

Abstract

This paper presents a clock interpolation structure with delay-locked loop (DLL) used for clock generation in high-speed ADCs. By adjusting the sampli......

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