Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs

Vanna-Iampikul, P; Shao, CJ; Lu, YC; Pentapati, S; Heo, Y; Choi, JS; Lim, SK

Vanna-Iampikul, P (通讯作者)，Georgia Inst Technol, Dept Elect & Comp Engn, Atlanta, GA 30332 USA.

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023; 42 (7): 2331

Abstract

3-D integration technology is one of the leading options to advance Moore's Law beyond conventional scaling. One of the 3-D integration choice is the ......

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