A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation

Ni, M; Wang, X; Li, FL; Wang, ZH

Li, FL (corresponding author), Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (7): 1416

Abstract

This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) anal......

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