VHDL implementation of FWL RLS algorithm

Bellizia, D; Monsurro, P; Trifiletti, A

Bellizia, D (reprint author), Univ Rome Sapienza, Dept Informat, Elect, Telecommun Engn, Rome, Italy.

2017 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), 2017; ( ):

Abstract

The Frisch-Waugh-Lovell (FWL) Recursive Least Squares (RLS) algorithm has been recently proposed as an RLS algorithm with lower computational cost and......

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