Synthesis of All-Digital Delay Lines

Moreno, A; Cortadella, J

Moreno, A (reprint author), Univ Politecn Cataluna, Dept Comp Sci, ES-08034 Barcelona, Spain.

2017 23RD IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC), 2017; ( ): 75

Abstract

The synthesis of delay lines (DLs) is a core task during the generation of matched delays, ring oscillator clocks or delay monitors. The main figure o......

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