SAT-based Redundancy Removal

Debnath, K; Murgai, R; Jain, M; Olson, J

Debnath, K (reprint author), Synopsys India Private Ltd, Bengaluru, India.

PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018; (): 315

Abstract

Logic optimization is an integral part of digital circuit design. It reduces design area and power consumption, and quite often improves circuit delay......

Full Text Link