Through-Silicon Via Capacitance-Voltage Hysteresis Modeling for 2.5-D and 3-D IC

Kim, DH; Kim, Y; Cho, J; Bae, B; Park, J; Lee, H; Lim, J; Kim, JJ; Piersanti, S; de Paulis, F; Orlandi, A; Kim, J

Kim, DH (reprint author), Korea Adv Inst Sci & Technol, Dept Elect Engn, Daejeon 34141, South Korea.

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2017; 7 (6): 925

Abstract

We propose, for the first time, an explicit semiconductor physics-based through-silicon via (TSV) capacitance-voltage (CV) model. The effect of TSV CV......

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