筛选条件 共查询到170条结果
排序方式
A Time-Interleaved 2nd-Order Delta Sigma Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (8)

This article presents a 4x time-interleaved (TI) 2nd-order discrete-time (DT) delta-sigma modulator (DSM). We propose a digital feed-forward extrapola......

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (5)

Physically unclonable function (PUF) has been increasingly used as a promising primitive for hardware security with a wide range of applications in th......

STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (6)

The emerging edge intelligence requires low-cost energy-efficient neural network (NN) processors. Supporting various types of edge NN models leads to ......

A Hybrid Single-Inductor Bipolar-Output DC-DC Converter With Floating Negative Output for AMOLED Displays

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (9)

This article presents a hybrid single-inductor bipolar-output (SIBO) dc-dc converter for active-matrix organic light-emitting diode (AMOLED) displays,......

A Single-Stage Dual-Output Regulating Rectifier With Hysteretic Current-Wave Modulation

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (9)

This article presents a 6.78-MHz single-stage dual-output regulating rectifier for miniaturizing the true wireless devices. The proposed rectifier top......

A Hybrid Boost Converter With Cross-Connected Flying Capacitors

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (7)

This article presents a monolithic hybrid boost converter suitable for a high conversion ratio (CR). It uses two inductors, two cross-connected flying......

A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (6)

This article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) incorporating v......

A W-Band Single-Antenna FMCW Radar Transceiver With Adaptive Leakage Cancellation

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (6)

This article presents a leakage cancellation architecture for single-antenna frequency-modulated continuous-wave (FMCW) radars at W-band. A shared ant......

A 70-mu W 1.35-mm(2) Wireless Sensor With 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (7)

This article presents a wireless multi-channel sensor interface circuit for emerging e-skin applications. The proposed interface circuit uses a CDMA-l......

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (9)

This article presents a computing-in-memory (CIM) structure aimed at improving the energy efficiency of edge devices running multi-bit multiply-and-ac......

Realization of In-Band Full-Duplex Operation at 300 and 4.2 K Using Bilateral Single-Sideband Frequency Conversion

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (5)

CMOS-integrated in-band full-duplex (IBFD) operation in wireless links and cryogenic quantum platforms was previously enabled by magnetic-free circula......

A 59-to-276-GHz CMOS Signal Generator Using Varactor-Less VCO and Dual-Mode ILFD

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (8)

An ultrawideband millimeter-wave (mm-Wave) and subterahertz (sub-THz) signal generator is proposed leveraging a varactor-less quad-band voltage-contro......

A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D Ultrasound System

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (6)

We present an area- and power-efficient application-specific integrated circuit (ASIC) for a miniaturized 3-D ultrasound system. The ASIC is designed ......

A Reconfigurable Non-Uniform Power-Combining V-Band PA With+17.9 dBm P-sat and 26.5% PAE in 16-nm FinFET CMOS

期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021; 56 (5)

This article presents the design of a dual-mode V-band power amplifier (PA) that enhances the efficiency at power back-off (PBO) using load modulation......

共170条页码: 1/12页15条/页